Particle Swarm Optimization Algorithm for Leakage Power Reduction in VLSI Circuits

Leela Rani Vanapalli

Abstract


 Leakage power is the dominant source of power dissipation in
nanometer technology. As per the International Technology Roadmap for
Semiconductors (ITRS) static power dominates dynamic power with the
advancement in technology. One of the well-known techniques used for
leakage reduction is Input Vector Control (IVC). Due to stacking effect in
IVC, it gives less leakage for the Minimum Leakage Vector (MLV) applied
at inputs of test circuit. This paper introduces Particle Swarm Optimization
(PSO) algorithm to the field of VLSI to find minimum leakage vector.
Another optimization algorithm called Genetic algorithm (GA) is also
implemented to search MLV and compared with PSO in terms of number of
iterations. The proposed approach is validated by simulating few test
circuits. Both GA and PSO algorithms are implemented in Verilog HDL
and the simulations are carried out using Xilinx 9.2i. From the simulation
results it is found that PSO based approach is best in finding MLV
compared to Genetic based implementation as PSO technique uses less
runtime compared to GA. To the best of the author’s knowledge PSO
algorithm is used in IVC technique to optimize power for the first time and
it is quite successful in searching MLV.


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References


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