Low-Power High-Speed Double Gate 1-bit Full Adder Cell

Authors

  • Raushan Kumar The Department of ECE, National Institute of Technology Arunachal Pradesh, P.O. Yupia, Arunachal Pradesh, 791112, India
  • Sahadev Roy The Department of ECE, National Institute of Technology Arunachal Pradesh, P.O. Yupia, Arunachal Pradesh, 791112, India http://orcid.org/0000-0002-9952-049X
  • Chandan Tilak Bhunia National Institute of Technology Arunachal Pradesh, P.O. Yupia, Arunachal Pradesh, 791112, India

Abstract

In this paper, we proposed an efficient full adder circuit using 16 transistors. The proposed high-speed adder circuit able to operate at very low voltage and maintain the proper output voltage swing and also balanced the power consumption and speed. Proposed design is based on CMOS mixed threshold voltage logic (MTVL) and implemented in 180nm CMOS technology). In the proposed technique the most time-consuming and power consuming XOR gates and multiplexor are designed using MTVL scheme. The maximum average power consumed by the proposed circuit is 6.94µW at 1.8V supply voltage and frequency of 500 MHz, which is less than other conventional methods. Power, delay, and area are optimized by using pass transistor logic and verified using SPICE simulation tool at desired broad frequency range. It is also observed that the proposed designs successfully utilized in many cases, especially whenever the lowest power consumption and delay are aimed.

Author Biographies

Raushan Kumar, The Department of ECE, National Institute of Technology Arunachal Pradesh, P.O. Yupia, Arunachal Pradesh, 791112, India

Pursuing her M.tech. studies in the Department of (ECE)

BTECH in (ECE)

 

Sahadev Roy, The Department of ECE, National Institute of Technology Arunachal Pradesh, P.O. Yupia, Arunachal Pradesh, 791112, India

Asst. Prof. Department of (ECE)

BTECH In (ECE)

M.TECH In (ECE)

PhD(VLSI)

Chandan Tilak Bhunia, National Institute of Technology Arunachal Pradesh, P.O. Yupia, Arunachal Pradesh, 791112, India

PhD in Engineering Prof ECE

Director of National Institute of Technology Arunachal Pradesh, P.O. Yupia, Arunachal Pradesh, 791112, India

 

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Published

2016-11-13

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Section

Microelectronics, nanoelectronics