A Method to Support Diagnostics of Dynamic Faults in Networks of Interconnections

Tomasz Garbolino


The article is devoted to the method facilitating the diagnostics of dynamic faults in networks of interconnection in systems-on-chips. It shows how to reconstruct the erroneous test response sequence coming from the faulty connection based on the set of signatures obtained as a result of multiple compaction of this sequence in the MISR register with programmable feedback. The Chinese reminder theorem is used for this purpose. The article analyzes in detail the various hardware realizations of the discussed method. The testing time associated with each proposed solution was also estimated. Presented method can be used with any type of test sequence and test pattern generator. It is also easily scalable to any number of nets in the network of interconnections. Moreover, it supports finding a trade-off between area overhead and testing time.

Full Text:



X. Aragones, J.L. González: “Noise Generation and Coupling Mechanisms in Deep-Submicron Ics”, IEEE Design & Test of Computers, vol.19, no.5, September-October 2002, pp.27-35. DOI: 10.1109/MDT.2002.1033789

M. Cuviello, S. Dey, X. Bai, Y. Zhao: “Fault modeling and simulation for crosstalk in system-on-chip interconnects”, [in:] 1999 IEEE/ACM international Conference on Computer-Aided Design, San Jose, California, USA, 7-11 November 1999, pp. 297-303. DOI: 10.1109/ICCAD.1999.810665

A. DeHon, H. Naeimi: “Seven strategies for tolerating highly defective fabrication”, IEEE Design & Test of Computers, Vol. 22, Iss. 4, July Aug. 2005, pp. 306 315. DOI: 10.1109/MDT.2005.94

IEEE Std 1500-2005, “IEEE Standard Testability Method for Embedded Core-based Integrated Circuits”, IEEE, Piscataway, NJ, USA, 2005. DOI: 10.1109/IEEESTD.2005.96465

T. Garbolino, M. Kopeć, K. Gucwa, A. Hławiczka: “Detection, localization and identification of interconnection faults using MISR compactor”, [in:]: Proceedings of IEEE Design and Diagnostics of Electronic Circuits and Systems Workshop, April 18 21, 2006. Institute of Electrical and Electronics Engineers, 2006, pp. 228-229. DOI: 10.1109/DDECS.2006.1649621

T. Garbolino, M. Kopeć, K. Gucwa, A. Hławiczka: “Multi-signature analysis for interconnect test”, [in:] Napieralski A. (ed.) Proceedings of the International Conference on Mixed Design of Integrated Circuits and Systems – MIXDES 2006, Gdynia, Poland, 22 24 June 2006, pp. 577 582. DOI: 10.1109/MIXDES.2006.1706646

A. Hławiczka, M. Kopeć: “Dependable testing of compactor MISR: an imperceptible problem?”, [in:] Proceedings of the 7th IEEE European Test Workshop, Corfu Greece 26 29 May 2006, pp. 31 36. DOI: 10.1109/ETW.2002.1029636

N. Koblitz: „A Course in Number Theory and Cryptography”, Graduate Texts in Math. No. 114, Springer-Verlag, New York, 1987. Second edition, 1994. DOI: 10.1007/978-1-4419-8592-7

A. Kologeski, C. Concatto, F. L. Kastensmidt, L. Carro: “ATARDS: An adaptive fault-tolerant strategy to cope with massive defects in Network-on-Chip interconnections”, [in:] Proc. 2012 IEEE/IFIP 20th International Conference on VLSI and System-on-Chip (VLSI-SoC), Santa Cruz, CA, USA, 7 10 October 2012, pp. 24 29. DOI: 10.1109/VLSI-SoC.2012.7332071

A. Kologeski, C. Concatto, F. L. Kastensmidt, L. Carro: “Fault-Tolerant Techniques to Manage Yield and Power Constraints in Network-on-Chip Interconnections”, [in:] VLSI-SoC: From Algorithms to Circuits and System-on-Chip Design, IFIP Advances in Information and Communication Technology, Vol. 418, 2013, pp. 144-161. DOI: 10.1007/978-3-642-45073-0_8

M. Kopeć, T. Garbolino, K. Gucwa, A. Hławiczka: “Test-per-clock detection, localization and identification of interconnect faults”, [in:] Proceedings of 11th IEEE European Test Symposium ETS 2006, Southampton, United Kingdom, 21-24 May 2006. Piscataway : Institute of Electrical and Electronics Engineers 2006, pp. 233-238. DOI: 10.1109/ETS.2006.45

M. Kopeć, T. Garbolino, K. Gucwa, A. Hławiczka: “On application of polynomial algebra for identification of dynamic faults in interconnects”. Electronics and Telecommunications Quarterly, Vol. 54, No. 1, 2008, pp. 29 41.

K.S.-M. Li, C. L. Lee, C. Su, J.E. Chen: “A unified approach to detecting crosstalk faults of interconnects in deep sub-micron VLSI”, [in:] Proceedings of 13th IEEE Asian Test Symposium, Kenting, Taiwan, 15 17 November, 2004, pp. 145 150. DOI: 10.1109/ATS.2004.19

W. Rajski, J. Rajski: “Modular compactor of test responses”, [in:] Proc. 24th IEEE VLSI Test Symposium (VTS), Berkeley, CA, USA, 30 April 4 May 2006, pp. 242 251. DOI: 10.1109/VTS.2006.48

J. Rajski, J. Tyszer: “Diagnosis of Scan Cells in BIST Environment”, IEEE Transactions on Computers, Vol. 48, No. 7, July 1999, pp. 724 731. DOI: 10.1109/12.780879

I. S. Reed, G. Solomon: “Polynomial Codes over Certain Finite Fields”, Journal of the Society for Industrial and Applied Mathematics, Vol. 8, Iss. 2, 1960, pp. 300 304. DOI: 10.1137/0108018

J. Rivoir: “Parallel Test Reduces Cost of Test More Effectively Than Just a Cheap Tester”, [in:] Proc. IEEE/CPMT/SEMI 29th International Electronics Manufacturing Technology Symposium – IEMT’04, San Jose, CA, USA, 14 16 July 2004, pp. 263 272. DOI: 10.1109/IEMT.2004.1321674

V. Shoup: “A Computational Introduction to Number Theory and Algebra”, 2nd Edition, Cambridge university Press, December 2008.

V. Shoup: “NTL: “A Library for doing Number Theory“, version 6.2.1, http://www.shoup.net/ntl/, 2014.

Y. Wu, S.M.I. Adham: „Scan Based BIST Fault Diagnosis”, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 18, No. 2, February 1999, pp. 203 21. DOI: 10.1109/43.743733


  • There are currently no refbacks.

International Journal of Electronics and Telecommunications
is a periodical of Electronics and Telecommunications Committee
of Polish Academy of Sciences

eISSN: 2300-1933