This paper proposes a unique method of an error detection and correction (EDAC) circuit, carried out using arithmetic logic blocks. The modified logic blocks circuit and its auxiliary components are designed with Boolean and block reduction technique, which reduced one logic gate per block. The reduced logic circuits were simulated and designed using MATLAB Simulink, DSCH 2 CAD, and Microwind CAD tools. The modified, 2:1 multiplexer, demultiplexer, comparator, 1-bit adder, ALU, and error correction and detection circuit were simulated using MATLAB and Microwind. The EDAC circuit operates at a speed of 454.676 MHz and a slew rate of -2.00 which indicates excellence in high speed and low-area.


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Joseph Crop Evgeni Krimer , Nariman Moezzi-Madani , Robert Pawlowski , Thomas Ruggeri 1 , Patrick Chiang 1 and Mattan Erez Error Detection and Recovery Techniques for Variation-Aware CMOS Computing: A Comprehensive Review. J. Low Power Electron. Appl. 2011, 1, pp 334-356.

Jani Mäkipää , Matthew J. Turnquist , Erkka Laulainen and Lauri Koskinen Timing-Error Detection Design Considerations in Subthreshold: An 8-bit Microprocessor in 65 nm CMOS LPEA 2012, 2(2), pp 180-196.

Varadan Savulimedu Veeravalli Fault tolerance for arithmetic and logic unit IEEE South eastcon 2009 Pages: 329 – 334.

S. H. Mozafari, M. Fazeli, S. Hessabi, S. G. Miremadi, "A Low Cost circuit level fault detection technique to Full Adder design", Electronics Circuits and Systems (ICECS) 2011 18th IEEE International Conference on, 2011, pp. 446-450.

Ryan C. Bickham, , Daniel B. Limbrick, William H. Robinson, Bharat L. Bhuva, “ An Analysis of Error Detection Techniques for Arithmetic Logic Units (ALUs) “RADECS 2010, IEEE Proceedings.

Shinjini Yadav and A. K. Singh Implementation of 32-Bit Fault Tolerance ALU using VHDL for Checking bit up to 6 Bits. International Journal of Research and Development in Applied Science and Engineering, Volume 10, Issue 2, July 2016, pp 1-7.

C. Senthilpari, G. Ramanamurthy, P. Velrajkumar An Efficient EPI and Energy Consumption of 32 bit ALU Using Shannon Theorem Based Adder Approach WSEAS TRANSACTIONS on CIRCUITS and SYSTEMS, Issue 7, Volume 10, July 2011, pp231-238.

J. Crop, R. Pawlowski and P. Chiang, "Regaining throughput using completion detection for error-resilient, near-threshold logic," DAC Design Automation Conference 2012, San Francisco, CA, 2012, pp. 974-979.

C Senthilpari, AK Singh, K Diwakar “Design of a low-power, high performance, 8× 8 bit multiplier using a Shannon-based adder cell” Microelectronics Journal 39 (5), pp 812-821.

Abhishek Rai, B Ananda Venkatesan M.Tech Scholar, “Analysis and Design of High Speed Low Power Comparator in ADC” © 2014 IJEDR | Volume 2, Issue 1 | ISSN: 2321-9939.

M. R. Kakoee, I. Loi and L. Benini, "Variation-Tolerant Architecture for Ultra Low Power Shared-L1 Processor Clusters," in IEEE Transactions on Circuits and Systems II: Express Briefs, vol. 59, no. 12, pp. 927-931, Dec. 2012.

C. H. Chen, D. Blaauw, D. Sylvester and Z. Zhang, "Design and Evaluation of Confidence-Driven Error-Resilient Systems," in IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 22, no. 8, pp. 1727-1737, Aug. 2014.

C.Senthilpari K.Diwakar KumarMunusamy J. SheelaFrancisca Layout parameter analysis in Shannon expansion theorem based on 32 bit adder circuit Engineering Science and Technology, an International Journal Volume 20, Issue 1, February 2017, Pages 35-40.

C Senthilpari “A Low-power and High-performance Radix-4 Multiplier Design Using a Modified Pass-transistor Logic Technique” IETE Journal of Research 57 (2), 149-155.

A. Rahimi, L. Benini and R. K. Gupta, "Variability Mitigation in Nanometer CMOS Integrated Systems: A Survey of Techniques From Circuits to Software," in Proceedings of the IEEE, vol. 104, no. 7, pp. 1410-1448, July 2016.


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