A 1.67 pJ/Conversion-step 8-bit SAR-Flash ADC Architecture in 90-nm CMOS Technology

Anil Khatak, Manoj Kumar, Sanjeev Dhull


A novice advanced architecture of 8-bit analog to
digital converter is introduced and analyzed in this work. The
structure of proposed ADC is based on the sub-ranging ADC
architecture in which a 4-bit resolution flash-ADC is utilized. The
proposed ADC architecture is designed by employing a comparator
which is equipped with common mode current feedback and
gain boosting technique (CMFD-GB) and a residue amplifier. The
proposed 8 bits ADC structure can achieve the speed of 140 megasamples
per second. The proposed ADC architecture is designed
at a resolution of 8 bits at 10 MHz sampling frequency. DNL and
INL values of the proposed design are -0.94/1.22 and -1.19/1.19
respectively. The ADC design dissipates a power of 1.24 mW
with the conversion speed of 0.98 ns. The magnitude of SFDR
and SNR from the simulations at Nyquist input is 39.77 and 35.62
decibel respectively. Simulations are performed on a SPICE based
tool in 90 nm CMOS technology. The comparison shows better
performance for the proposed ADC design in comparison to
other ADC architectures regarding speed, resolution and power

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