Producing Random Bits with Delay-Line Based Ring Oscillators

Authors

  • Mieczysław Jessa Poznań University of Technology, Faculty of Electronics and Telecommunications
  • Łukasz Matuszewski Poznań University of Technology, Faculty of Electronics and Telecommunications

Abstract

One of the sources of randomness for a random bit generator (RBG) is jitter present in rectangular signals produced by ring oscillators (ROs). This paper presents a novel approach for the design of delays used in these oscillators. We suggest using delay elements made on carry4 primitives instead of series of inverters or latches considered in the literature. It enables the construction of many high frequency ring oscillators with different nominal frequencies in the same field programmable gate array (FPGA). To assess the unpredictability of bits produced by RO-based RBG, the restarts mechanism, proposed in earlier papers, was used. The output sequences pass all NIST 800-22 statistical tests for smaller number of ring oscillators than the constructions described in the literature. Due to the number of ROs with different nominal frequencies and the method of construction of carry4 primitives, it is expected that the proposed RBG is more robust to cryptographic attacks than RBGs using inverters or latches as delay element.

References

W. T. Holman, J. A. Connelly, and A. B. Downlatabadi, “An integrated analog/digital random noise source,” IEEE Transactions on Circuits and Systems I: Fundamental Theory and Applications, vol. 44, pp. 521–528, June 1997.

V. Bagini and M. Bucci, “A Design of reliable true random number generator for cryptographic applications,” in Proceedings of Workshop Cryptographics Hardware Embedded Systems, CHES’1999, Heidelberg, 1999, pp. 204–218, LNCS 1717.

C. S. Petrie and J. A. Connelly, “The sampling of noise for random generation,” Proceedings of the 50th International Symposium on Circuits and Systems ISCAS’1999, vol. 6, pp. 26–29, 1999.

M. Bucci, L. Germani, R. Luzzi, P. Tommasimo, A. Trifiletti, and M. Varanonuovo, “A high-speed IC random-number source for smartcard microcontrollers,” IEEE Transactions on Circuits and Systems I: Fundamental Theory and Applications, vol. 50, pp. 1373–1380, November 2003.

J. Holleman, S. Bridges, B. P. Otis, and C. Diorio, “A 3 μw cmos true random number generator with adaptive floating-gate offset cancellation,” IEEE Journal of Solid-State Circuits, vol. 43, pp. 1324–1336, May 2008.

M. J. Bellido et al., “A simple binary random number generator: New appoaches for CMOS VLSI,” Proceedings of the 35th Midwest

Symposium on Circuits and Systems, vol. 1, pp. 127–129, 1992.

M. Epstein, L. Hars, R. Krasinski, M. Rosner, and H. Zheng, “Design and implementation of a true random number generator based on digital circuit artifacts,” in Proceedings of Workshop Cryptographics Hardware Embedded Systems, CHES’2003, 2003, pp. 152–165, LNCS 2779.

I. Vasyltsov, E. Hambardzumyan, Y.-S. Kim, and B. Karpinskyy, “Fast digital RBG based on metastable ring oscillator,” in Proceedings of Workshop Cryptographics Hardware Embedded Systems, CHES’2008,

, pp. 164–180, LNCS 5154.

S. Srinivasan, S. Mathew, V. Erraguntla, and R. Krishnamurthy, “A 4Gbps 0.57pJ/bit Process-Voltage-Temperature Variation Tolerant all-Digital True Random Number Generator in 45nm CMOS,” in Proceedings of 22nd International Conference on VLSI Design, 2009, pp. 301–306.

M. Varchola and M. Drutarovsky, “New high entropy element for FPGA based true random number generators,” in Proceedings of Workshop Cryptographics Hardware Embedded Systems, CHES’2010, 2010, pp 351–365, LNCS 6225.

G. Bernstein and M. A. Lieberman, “Secure random number generation using chaotic circuits,” IEEE Transactions on Circuits and System,vol. 37, pp. 1157–1164, Spetember 1990.

R. Bernardini and G. Cortelazzo, “Tools for designing chaotic systems for secure random number generation,” IEEE Transactions on Circuits and Systems I: Fundamental Theory and Applications, vol. 48, pp. 552–564, May 2001.

T. Stojanovski and L. Kocarev, “Chaos-based random number generators – Part I: Analysis,” IEEE Transactions on Circuits and Systems I:Fundamental Theory and Applications, vol. 48, pp. 281–288, March 2001.

T. Stojanovski, J. Pihl, and L. Kocarev, “Chaos-based random number generators – Part II: Practical realization,” IEEE Transactions on Circuits and Systems I: Fundamental Theory and Applications, vol. 48, pp. 382– 385, March 2001.

M. E. Yalc¸in, J. A. K. Suykens, and J. Vandewalle, “True bit generation from a double-scroll attractor,” IEEE Transactions on Circuits and Systems I, Regular Papers, vol. 51, pp. 1395–1404, July 2004.

S. Callegari, R. Rovatti, and G. Setti, “Embeddable ADC-based true random number generator for cryptographic applications exploiting

nonlinear signal processing and chaos,” IEEE Transactions on Signal Processing, vol. 53, pp. 793–805, February 2005.

S. Callegari, R. Rovatti, and G. Setti “First direct implementation of true random source on programmable hardware,” International Journal of Circuit Theory and Applications, vol. 33, pp. 1–16, 2005.

M. Drutarovsky and P. Galajda, “Chaos-based true random number generator embedded in a mixed-signal reconfigurable hardware,” Journal of Electrical Engineering, vol. 57, pp. 218–225, April 2006.

S. Ergun and S. Ozog, “Truly random number generator based on a nonautonomous chaotic oscillator,” International Journal of Electronics and Communications, vol. 61, pp. 235–242, April 2007.

C. S. Petrie and J. A. Connelly, “Modelling and simulation of oscillator based random number generators,” Proceedings of the 47th International Symposium on Circuits and Systems ISCAS’1996, vol. 4, pp. 324–327, 1996.

C. S. Petrie and J. L. Connelly, “A noise-based IC random number generator for applications in Cryptography,” IEEE Transactions on

Circuits and Systems I: Fundamental Theory and Applications, vol. 47, pp. 615–621, May 2000.

M. Bucci, L. Germani, R. Luzzi, A. Trifiletti, and M. Varnonuovo, “A high-speed oscillator-based truly random number source for cryptographic applications on a smartcard IC,” IEEE Transactions on Computers, vol. 52, pp. 403–409, April 2003.

B. Jun and B. Kocher, The Intel random number generator. San Francisco, CA: Cryptography Research Inc., April 1999, white paper for Intel Corp. Available at:

http://www.cryptography.com/resources,whitepapers/IntelRNG.pdf.

P. Kohlbrenner and K. Gay, “An embedded true random number generator for FPGAs,” in Proceedings of the 2004 ACM/SIGDA 12th International Symposium on FPGAs, FPGA’04, 2004, pp. 71–77.

J. D. Goli´c, “New methods for digital generation and post processing of random data,” IEEE Transactions on Computers, vol. 55, pp. 1217–1229, October 2006.

M. Dichtl and J. D. Golic, “High speed true random number generation with logic gates only,” in Proceedings of Workshop Cryptographics Hardware Embedded Systems, CHES’2007, 2007, pp. 45–62, LNCS 4727.

B. Valtchanov, A. Aubert, F. Bernard, and V. Fischer, “Modeling and observing the jitter in ring oscillators implemented in FPGAs,” in

Proceedings of IEEE Workshop on Design and Diagnostics of Electronic

Circuits and Systems, DDECS’08, 2008, pp. 1–6.

B. Valtchanov, V. Fischer, A. Aubert, and F. Bernard, “Characterization of randomness sources in ring oscillator-based true random number generators in FPGAs,” in Proceedings of IEEE Workshop on Design and Diagnostics of Electronic Circuits and Systems, DDECS’10, 2010, pp. 48–53.

M. Baudet, D. Lubicz, J. Micolod, and A. Tassiaux, “On the security of oscillator-based random number generators,” Journal of Cryptology, vol. 24, pp. 398–425, 2011.

B. Sunar, W. J. Martin, and D. R. Stinson, “A provably secure true random number generator with built-in tolerance to active attacks,” IEEE Transactions on Computers, vol. 56, pp. 109–119, January 2007.

K. Wold and C. H. Tan, “Analysis and enhancement of random number generator in FPGA based on oscillator rings,” International Journal of Reconfiugurable Computing, vol. 2009, pp. 1–8, 2009.

K. Wold and S. Petrovi´c, “Optimizing speed of a true random number generator in FPGA by spectral analysis,” in Proceedings of Fourth International Conference on Computer Sciences and Convergence Information Technology, ICCIT’09, 2009, pp. 1105–1110.

N. Bochard, F. Bernard, and V. Fischer, “Observing the randomness in RO-based RBG,” in Proceedings of International Conference on Reconfigurable Computing and FPGAs, ReConFig 2009, 2009, pp. 237–242.

M. Jessa and M. Jaworski, “Randomness of a combined RBG based on the ring oscillator sampling method,” in Proceedings of International Conference on Signals and Electronic Systems, ICSES’10, 2010, pp. 323–326.

M. Jessa and L. Matuszewski, “Enhancing the Randomness of a Combined True Random Number Generator Based on the Ring Oscillator Sampling Method,” in Proceedings of International Conference on

ReConFigurable Computing and FPGAs, ReConFig’2011, 2011, pp. 274–279.

K. Wold and S. Petrovi´c, “Security properties of oscillator rings in true random number generators,” in Proceedings of 15th International Symposium on Components, Circuits, Devices and Systems, 2012, pp. 145–150.

A. T. Markettos and S. M. Moore, “The frequency injection attack on ring-oscillator-based true random number generators,” in Proceedings of Workshop Cryptographics Hardware Embedded Systems, CHES’2009,

September 2009, pp. 317–331, LNCS 5747.

M. Jessa and L. Matuszewski, “The Use of Delay Lines in a Ring- Oscillator-Based Combined True Random Number Generator,” in Proceedings of International Conference on Signals and Electronic Systems,

ICSES’12, 2012, article 51.

Ü. Güler, S. Ergün, and G. Dündar, “A digital IC random number generator with logic gates only,” in Proc. of 17th IEEE International Conference on Electronics, Circuits, and Systems (ICECS), December 2010, pp. 239–242.

A. Hajimiri, S. Limotyraksis, and T. H. Lee, “Jitter and Phase Noise in Ring Oscillators,” IEEE Journal of Solid-State Circuits, vol. 34, no. 6, June 1999.

J. Guckenheimer and P. Holmes, Nonlinear Oscillations, Dynamical Systems, and Bifurcation of Vector Fields. New York: Springer, 1983. [42] “Virtex-5 Libraries Guide for HDL Designs,”

http://www.xilinx.com/itp/xilinx10/books/docs/virtex5 hdl/virtex5 hdl.pdf.

C. Favi and E. Charbon, “A 17ps Time-to-Digital Converter Implemented in 65nm FPGA Technology,,” in Proceedings of the ACM/SIGDA international symposium on Field programmable gate arrays, FPGA’09, Monterey, California, USA, February 2009.

A. Rukhin, J. Soto, J. Nechvatal, M. Smid, E. Barker, S. Leigh, M. Levenson, M. Vangel, D. Banks, A. Heckert, J. Dray, and S. Vo, A

statistical test suite for random and pseudorandom number generators for cryptographic applications. NIST special publication 800-22, Revised: April 2010, USA, Available at: http://csrc.nist.gov/rng

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2014-09-24

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