PyHLS: Intermediate Representation for Versatile High-Level Synthesis

Abstract

High-Level Synthesis (HLS) has become an estab-
lished methodology to accelerate the development of FPGA-
based systems by allowing algorithms to be written in high-level
languages (HLLs) such as C/C++ or Python. Yet, for real-
time physics experiments—including fusion plasma diagnostics,
high-energy physics (HEP) detectors, and rare-event astro-
physical triggers—conventional HLS still falls short in three
essential aspects: determinism, portability, and auditability.
Pragmas embedded in HLL code blur the separation between
algorithmic intent and implementation details, coupling scien-
tific software to a particular device or compiler version. This
is particularly problematic in long-lived scientific projects such
as ITER or the Pierre Auger Observatory, where systems must
remain functional and maintainable over decades [4]–[6].
To address these challenges, we propose an Intermediate
Representation (IR)-centric HLS flow—PyHLS—that explic-
itly introduces an abstraction layer between algorithm and
Register-Transfer Level (RTL) design. The IR centralizes all
performance-critical aspects: timing contracts (initiation inter-
val, latency, jitter), concurrency (loop unrolling, pipelining),
memory layout (banking, tiling, port allocation), and resource
binding (DSPs, BRAMs, AI tiles). In this model, the algorithm
is expressed in clean, testable Python code [1], [2], while
device-specific optimizations are described in a structured
IR graph. This IR is then lowered into a reusable VHDL
microinstruction library [3], which serves as a portable middle
layer across devices. By versioning and auditing IR graphs
and instruction streams, PyHLS ensures reproducibility and
traceability—critical properties in scientific computing where
results must be verifiable years after deployment.
The methodology builds upon earlier work in Python-
based high-level synthesis, parameterizable metamodels, and
algorithmic synthesis with multi-level compilers [8], [9], [11].
It incorporates systematic design space exploration (DSE),
allowing parameter sweeps over IR attributes and early fea-
sibility checks. The flow is complemented by a cycle-accurate
microinstruction emulator, which validates both functionality
and timing contracts before vendor toolchains are invoked,
reducing iteration time and catching infeasible designs early.
We demonstrate the motivation and applicability of this
approach in two demanding domains. First, in plasma diagnos-
tics at JET/ITER, where spectrometer and data acquisition
systems must combine high bandwidth with deterministic
latency [6]. Second, in trigger pipelines for astroparticle physics,
where artificial neural networks (ANNs) and fuzzy-logic al-
gorithms have been implemented directly in FPGA logic to
discriminate rare events from large backgrounds [4], [5]. These
use-cases highlight the need for explicit IR-level contracts and
modularity: the same high-level algorithm must be portable
across device generations, yet adapted to exploit specialized
hardware resources such as DSP slices, systolic AI engines, or
high-bandwidth memories.
The contribution of this work is therefore threefold:

1) We formalize the role of an explicit IR in HLS, decoupling
algorithms from implementation decisions and introduc-
ing contract-driven determinism.
2) We present a reusable VHDL microinstruction library
and emulator that stabilize implementation and provide
auditable artifacts.
3) We show how PyHLS extends naturally to heterogeneous
FPGAs, mapping operators to emerging AI/ML blocks
while maintaining scientific reproducibility and portabil-
ity across decades.
By unifying algorithmic specification, IR-based parameter-
ization, and reusable microinstructions, PyHLS establishes a
sustainable methodology for real-time physics experiments and
beyond. In short: write the science once, retarget the hardware
many times.